(a) Field of the Invention
The present invention relates to a low dissipation inverter circuit and, more particularly, to an inverter circuit having a charge recovery function.
(b) Description of the Related Art
The recent design for large-scale semiconductor integrated circuit is generally based on synchronizing operation of the integrated circuit using a clock signal. There is a tendency that the clock signal line for propagating the clock signal has a larger parasitic capacitance. For this reason, the electric power consumed by charge/discharge of the clock signal line amounts as high as several watts, for example.
On the other hand, a semiconductor integrated circuit is known which has low-threshold MOS transistors in a logic circuit for operating the circuit at a high speed. However, the low-threshold transistors generally suffer from a problem of large penetrating current. In order to reduce the penetrating current flowing through the low-threshold MOS transistors, there is a proposal that the semiconductor integrated circuit have four source lines including global/local power lines and global/local ground lines. A high-threshold MOS transistor disposed between the global power line and the local power line or between the global ground line and the local ground line separates the local power line and the local ground line from the global power line and the global ground line, respectively, during a sleep mode of the semiconductor integrated circuit to reduce power dissipation.
In the proposed configuration, however, the high-threshold MOS transistor has a large gate width, which may amount to tens of millimeters, for example, or may amount to 10 to 30% of the total gate width of all the MOS transistors disposed in the logic circuit. The larger gate width MOS transistor in fact consumes large electric power, thereby limiting the amount of power saving.
In any case, the power saving is the most important subject for the semiconductor integrated circuits. In view of the power saving in the semiconductor integrated circuit, the present invention is to provide a low dissipation inverter circuit because the inverter circuit is one of the most fundamental circuit block used in the semiconductor integrated circuits for driving a large-capacitance load.
Referring to FIG. 1 showing a conventional inverter circuit, a first inverter section 21 and a second inverter section 22 are cascaded. The inverter circuit receives an input signal IN supplied through an input terminal 13, to output a pair of complementary signals including a non-inverting output signal OUT and an inverting output signal OUTB through respective output terminals 15 and 16.
In the inverter circuit of FIG. 1, a first case is assumed such that an input signal IN supplied to the input terminal 13 rises from a low level to a high level. The initial state of the inverter circuit is such that the input terminal 13 and the non-inverting output terminal 15 assume a low level, whereas the inverting output terminal 16 assumes a high level. After the input signal rises to a high level, nMOSFET MNC1 and pMOSFET MPC1 in the first inverter section 21 are turned on and off, respectively, whereby the electric charge stored on the inverting output terminal 16 and the input node of the second inverter section 22 is discharged through the nMOSFET MNC1. Thus, the potential of the output terminal 16 and the input node of the second inverter section 22 falls from a high level to a low level, whereby pMOSFET MPC2 and nMOSFET MNC2 are turned on and off, respectively. Thus, the output terminal 15 is supplied with electric charge from the VDD power line 12 to assume a high level. In the operation as described above, the electric charge stored on the inverting output terminal 16 and the input node of the second inverter section 22 is discharged to the ground line 11, whereas the electric charge for charging the non-inverting output terminal 15 is supplied from the VDD power line 12.
Assuming that the input signal falls from a high level to a low level in a second case, the initial potential on each terminal is reversed to that in the first case. After the input signal IN falls to a low level, pMOSFET MPC1 and nMOSFET MNC1 in the first inverter section 11 are turned on and off, respectively, whereby the inverting output terminal 16 and the input of the second inverter section 22 are supplied with electric charge from the VDD power line 12 through pMOSFET MPC1 to assume a high level, whereby nMOSFET MNC2 and pMOSFET MPC2 in the second inverter section 22 are turned on and off, respectively. Thus, the electric charge stored on the non-inverting output terminal 15 is discharged to the ground line 11 through nMOSFET MNC2 to assume a low level. In the operation of the second case, the electric charge for charging the inverting output terminal 16 and the input node of the second inverter section 22 is supplied from the VDD power line 12, whereas the electric charge stored on the non-inverting output terminal 15 is discharged to the ground line 11.
In the conventional inverter circuit, the charge for raising the potential on the internal nodes and the output terminals of the inverter circuit is supplied from the power line, whereas all the charge stored on the internal nodes and the output terminals is discharged to the ground line without reuse.